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cy15e064q 64-kbit (8k 8) serial (spi) automotive f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-10028 rev. *b revised april 12, 2017 64-kbit (8k 8) serial (spi) automotive f-ram features 64-kbit ferroelectric random access memory (f-ram) logically organized as 8k 8 ? high-endurance 10 trillion (10 13 ) read/writes ? 121-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface (spi) ? up to 16mhz frequency ? direct hardware replacement for serial flash and eeprom ? supports spi mode 0 (0, 0) and mode 3 (1, 1) sophisticated write protection scheme ? hardware protection using the write protect (wp ) pin ? software protection using write disable instruction ? software block protection for 1/4, 1/2, or entire array low power consumption ? 300 ? a active current at 1 mhz ? 10 ? a (typ) standby current at +85 ? c voltage operation: v dd = 4.5 v to 5.5 v automotive-e temperature: ?40 ? c to +125 ? c 8-pin small outline integrated circuit (soic) package aec q100 grade 1 compliant restriction of hazardous substances (rohs) compliant functional description the cy15e064q is a 64-kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 121 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash, eeprom, and other nonvolatile memories. unlike serial flash and eeprom, the cy15e064q performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance compared with other nonvolatile memories. the cy15e064q is capable of supporting 10 13 read/write cycles, or 10 millio n times more write cycles than eeprom. these capabilities make the cy15e064q ideal for nonvolatile memory applications requirin g frequent or rapid writes. examples range from data collecti on, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or eeprom can cause data loss. the cy15e064q provides substantial benefits to users of serial eeprom or flash as a hardwa re drop-in replacement. the cy15e064q uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the device specifications are guaranteed ov er an automotive-e temperature range of ?40 ? c to +125 ? c. instruction decoder clock generator control logic write protect instruction register address register counter 8 k x 8 f-ram array 13 data i/ o register 8 nonvolatile status register 3 wp cs hold sck so si logic block diagram
cy15e064q document number: 002-10028 rev. *b page 2 of 20 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 functional overview ........................................................ 4 memory architecture ........................................................ 4 serial peripheral interface ? spi bus .............................. 4 spi overview ............................................................... 4 spi modes ................................................................... 5 power up to first access .... ........................................ 6 command structure .................................................... 6 wren - set write enable latch .......... .............. ......... 6 wrdi - reset write enable latch ............................... 6 status register and write prot ection ............................. 6 rdsr - read status register ..................................... 7 wrsr - write status register .................................... 7 memory operation ............................................................ 8 write operation ........................................................... 8 read operation ........................................................... 8 hold pin operation ................................................... 9 endurance ................................................................. 10 maximum ratings ........................................................... 11 operating range ............................................................. 11 dc electrical characteristics ........................................ 11 data retention and endurance ..................................... 12 example of an f-ram life time in an aec-q100 automotive application ..................... 12 capacitance .................................................................... 12 thermal resistance ........................................................ 12 ac test conditions ........................................................ 12 ac switching characteristics ....................................... 13 power cycle timing ....................................................... 15 ordering information ...................................................... 16 ordering code definitions ..... .................................... 16 package diagram ............................................................ 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc? solutions ...................................................... 20 cypress developer community ................................. 20 technical support ................. .................................... 20
cy15e064q document number: 002-10028 rev. *b page 3 of 20 pinout figure 1. 8-pin soic pinout pin definitions pin name i/o type description cs input chip select . this active low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and tristate s the output. when low, the device internally activates the sck signal. a falling edge on cs must occur before every opcode. sck input serial clock . all i/o activity is synchronized to the seri al clock. inputs are latched on the rising edge and outputs occur on the falling edge. because the device is synchronous, the clock frequency may be any value between 0 and 16 mhz and may be interrupted at any time. si [1] input serial input . all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driv en to a valid logic level to meet idd specifications. so [1] output serial output . this is the data output pin. it is driven dur ing a read and remains tristated at all other times including when hold is low. data transitions are driven on the falling edge of the serial clock. wp input write protect . this active low pin prevents write oper ation to the status register when wpen is set to ?1?. this is critical because other write protection features are controlled through the status register. a complete explanation of write protection is provided in status register and write protection on page 7 . this pin must be tied to v dd if not used. note that the function of wp is different from the fm25040 where it prevents al l writes to the part. hold input hold pin . the hold pin is used when the host cpu must in terrupt a memory operation for another task. when hold is low, the current oper ation is suspended. the device ignores any transition on sck or cs . all transitions on hold must occur while sck is low. this pin must be tied to v dd if not used. v ss power supply ground for the device. must be connected to the gr ound of the system. v dd power supply power supply input to the device. hold sck 1 2 3 4 5 cs 8 7 6 v dd si so top view not to scale v ss wp note 1. si may be connected to so for a single pin data interface .
cy15e064q document number: 002-10028 rev. *b page 4 of 20 functional overview the cy15e064q is a serial f-ram memory. the memory array is logically organized as 8,192 8 bits and is accessed using an industry standard serial peripheral interface (spi) bus. the functional operation of the f-ram is similar to serial flash and serial eeproms. the majo r difference between the cy15e064q and a serial flash or eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the cy15e064q, the user addresses 8k locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a tw o-byte address. the upper 3 bits of the address range are 'don't care' values. the complete address of 13 bits specifies each byte address uniquely. most functions of the cy15e064q are either controlled by the spi interface or handled by on-board circuitry. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. th at is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted in to the device, a write operation is complete. this is explained in more detail in the interface section. note the cy15e064q contains no power management circuits other than a simple internal power-on reset circuit. it is the user?s responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip enable active. serial peripheral interface ? spi bus the cy15e064q is a spi slave device and operates at speeds up to 16 mhz. this high-speed serial bus provides high-performance serial communication to a spi master. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcon trollers that do not. the cy15e064q operates in spi mode 0 and 3. spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), a nd serial clock (sck) pins. the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on the spi bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated, the first byte transferred from the bus master is the opcode. followin g the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can be issued. the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on a spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of t he slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchronize d with this clock. spi slave the spi slave device is activated by the master through the chip select line. a slave device gets th e sck as an input from the spi master and all the communicat ion is synchronized with this clock. an spi slave never in itiates a communication on the spi bus and acts only on the instruction from the master. the cy15e064q operates as an spi slave and may share the spi bus with other spi slave devices. chip select (cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) the serial clock is generated by the spi master and the communication is synchronized with this clock after cs goes low. the cy15e064q enables spi modes 0 and 3 for data communication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefor e, the first rising edge of sck signifies the arrival of the first bit (msb) of a spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck. data transmission (si/so) the spi data bus consists of two lines, si and so, for serial data communication. si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to t he slave through the si pin, while
cy15e064q document number: 002-10028 rev. *b page 5 of 20 the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the cy15e064q has two separate pins for si and so, which can be connected with the master as shown in figure 2 . for a microcontroller that has no dedicated spi bus, a general-purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the hold and wp pins. figure 3 shows such a configuration, which uses only three pins. most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 64-kbit serial f-ram requires a 2-byte address for any read or write operation. because the address is only 13 bits, the first three bits which are fed in are ignored by the device. although these three bits are ?don?t care?, cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. cy15e064q uses the standard opcodes for memory accesses. invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of cs , and the so pin remains tristated. status register cy15e064q has an 8-bit status register. the bits in the status register are used to configure the device. these bits are described in table 3 on page 7 . spi modes cy15e064q may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck. figure 2. system configuration with spi port cs1 cs2 hold1 hold2 cy15e064q cy15e064q wp1 wp2 sck si so sck si so cs hold wp cs hold wp sck mosi miso spi microcontroller figure 3. system coniguration witout spi port cy15e064q microcontroller sck si so cs hold wp p1.2 p1.1 p1.0
cy15e064q document number: 002-10028 rev. *b page 6 of 20 the two spi modes are shown in figure 4 and figure 5 . the status of the clock when the bus ma ster is not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 the device detects the spi mode fr om the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. power up to first access the cy15e064q is not accessible for a t pu time after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first cs low. command structure there are six commands, called opcodes, that can be issued by the bus master to the cy15e064q. they are listed in table 1 . these opcodes control the functions performed by the memory. wren - set write enable latch the cy15e064q will power up wi th writes disabled. the wren command must be issued before any write operation. sending the wren opcode allows the user to issue subsequent opcodes for write operations. these incl ude writing the status register (wrsr) and writing the memory (write). sending the wren opcode causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of t he latch. wel = ?1? indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit ? only the wren opcode can set this bit. the wel bit will be aut omatically cleared on the rising edge of cs following a wrdi, a wrsr, or a write operation. this prevents further writes to t he status register or the f-ram array without another wren command. figure 6 illustrates the wren command bus configuration. wrdi - reset write enable latch the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel is equal to ?0?. figure 7 illustrates the wrdi command bus configuration. figure 4. spi mode 0 figure 5. spi mode 3 table 1. opcode commands name description opcode wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b lsb msb 76543210 cs sck si 01 2 3 4 5 67 cs sck si 765432 10 lsb msb 01 2 3 4 5 67 figure 6. wren bus configuration figure 7. wrdi bus configuration 0 0 0 0 0 1 1 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 00 1
cy15e064q document number: 002-10028 rev. *b page 7 of 20 status register and write protection the write protection features of the cy15e064q are multi-tiered and are enabled through the status register. the status register is organized as follows. (the default value shipped from the factory for bits in the status register is ?0?.) bits 0 and 4-6 are fixed at ?0?; none of these bits can be modified. note that bit 0 (?ready or write in progress? bit in serial flash and eeprom) is unnecessary, as the f-ram writes in real-time and is never busy, so it reads out as a ?0?. the bp1 and bp0 control the software write-protection f eatures and are nonvolatile bits. the wel flag indicates the state of the write enable latch. attempting to directly write the we l bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of me mory that are write- protected as shown in ta b l e 4 . the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the write protect enable bit (wpen) in the status register controls the effect of the hardware write protect (wp ) pin. when the wpen bit is set to ?0?, the status of the wp pin is ignored. when the wpen bit is set to ?1?, a low on the wp pin inhibits a write to the status register. thus the status register is write-protected only when wpen = ?1? and wp = ?0?. ta b l e 5 summarizes the write protection conditions. rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading the status register provides information about the current state of the write-protection features. fo llowing the rdsr opcode, the cy15e064q will return one byte with the contents of the status register. wrsr - write status register the wrsr command allows the spi bus master to write into the status register and change th e write protect configuration by setting the wpen, bp0 and bp1 bits as required. before issuing a wrsr command, the wp pin must be high or inactive. note that on the cy15e064q, wp only prevents writing to the status register, not the memory array. before sending the wrsr command, the user must send a wren command to enable writes. executing a wrsr command is a write operation and therefore, clears the write enable latch. table 2. status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) x (0) x (0) x (0) bp1 (0) bp0 (0) wel (0) x (0) table 3. status register bit definition bit definition description bit 0 don?t care this bit is non-writable and always returns ?0? upon read. bit 1 (wel) write enable latch wel indicates if the device is write enabled. this bit defaults to ?0? (disabled) on power-up. wel = ?1? --> write enabled wel = ?0? --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details, see ta b l e 4 . bit 3 (bp1) block protect bit ?1? used for block protection. for details, see ta b l e 4 . bit 4-6 don?t care these bits are non-writable and always return ?0? upon read. bit 7 (wpen) write protect enable bit used to ena ble the function of write protect pin (wp ). for details, see ta b l e 5 . table 4. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper 1/4) 1 0 1000h to 1fffh (upper 1/2) 1 1 0000h to 1fffh (all) table 5. write protection wel wpen wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected
cy15e064q document number: 002-10028 rev. *b page 8 of 20 memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash and eeproms, the cy15e064q can perform sequential writes at bus speed. no page register is needed and any number of sequential wr ites may be performed. write operation all writes to the memory begin with a wren opcode. the write opcode is followed by a two-byte address containing the 13-bit address (a12?a0) of the first data byte to be written into the memory. the upper three bits of the two-byte address are ignored. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps cs low. if the last address of 1fffh is re ached, the counter will roll over to 0000h. data is written msb first. the rising edge of cs terminates a write operation. a write operation is shown in figure 10 on page 9 . note when a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. eeproms use page buffers to in crease their write throughput. this compensates for the technology's inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the eighth clock). this allows any number of bytes to be written without page buffer delays. note if the power is lost in the mi ddle of the write operation, only the last completed byte will be written. read operation after the falling edge of cs , the bus master can issue a read opcode. following the read command is a two-byte address containing the 13-bit address (a12?a0) of the first byte of the read operation. the upper three bits of the address are ignored. after the opcode and address are issued, the device drives out the read data on the next eight clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and cs is low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of cs terminates a read operation and tristates the so pin. a read operation is shown in figure 11 on page 9 . figure 8. rdsr bus configuration figure 9. wrsr bus configuration (wren not shown) cs sck so 01234567 si 000001 0 0 1 hi-z 012345 67 lsb d0 d1 d2 d3 d4 d5 d6 msb d7 opcode data cs sck so 0123 4567 si 00 00000 1 msb lsb d2 d3 d7 hi-z 012345 67 opcode data x x x x x
cy15e064q document number: 002-10028 rev. *b page 9 of 20 hold pin operation the hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the hold pin low while sck is low, the current operati on will pause. taking the hold pin high while sck is low will resume an operation. the transitions of hold must occur while sck is low, but the sck and cs pin can toggle during a hold state. figure 10. memory write (wren not shown) figure 11. memory read ~ ~ cs sck so 01234 5 6 70 7 6 5 4 3 2 1 1213141501234567 msb lsb data d0 d1 d2 d3 d4 d5 d6 d7 si opcode 0000001 x x x a12 a11 a9 0 a10 a8 a3 a1 a2 a0 13-bit address msb lsb hi-z ~ ~ cs sck so 01 23456 70 7 6 5 4 3 2 1 12131415012345 6 7 msb lsb data si opcode 0000001 x x x a12 a11 a9 1 a10 a8 a3 a1 a2 a0 13-bit address msb lsb d0 d1 d2 d3 d4 d5 d6 d7 hi-z figure 12. hold operation [2] cs sck hold so ~ ~ ~ ~ si valid in valid in note 2. figure shows hold operation for input mode and output mode.
cy15e064q document number: 002-10028 rev. *b page 10 of 20 endurance the cy15e064q devices are capabl e of being accessed at least 10 13 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architec ture is based on an array of rows and columns of 1k rows of 64-bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. ta b l e 6 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data stream. this causes each byte to experience one endurance cycle through the loop. f-ram read and write endurance is virtually unlimited even at a 16 mhz clock rate. table 6. time to reach endurance limit for repeating 64-byte loop sck freq (mhz) endurance cycles/sec endurance cycles/year years to reach limit 4 7,480 2.36 10 11 42.3 1 1,870 5.88 10 10 170.1
cy15e064q document number: 002-10028 rev. *b page 11 of 20 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +150 ? c maximum accumulated storage time at 150 c ambient temperature ................................. 1000 h at 125 c ambient temperature ................................11000 h at 85 c ambient temperature .............................. 121 years ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on v dd relative to v ss .........?1.0 v to +7.0 v input voltage ............. ?1.0 v to +7.0 v and v in < v dd +1.0 v dc voltage applied to outputs in high z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ............................... 1.0 w surface mount lead soldering temperature (3 seconds) .......................... +260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma electrostatic discharge voltage [3] human body model (aec-q100-002 rev. e) ....................... 2 kv charged device model (aec-q100-011 rev. b) ................. 500 v latch up current ..................................................... > 140 ma operating range range ambient temperature (t a ) v dd automotive-e ?40 ? c to +125 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [4] max unit v dd power supply 4.5 5.0 5.5 v i dd v dd supply current sck toggling between v dd ? 0.3 v and v ss , other inputs v ss or v dd ? 0.3 v. so = open. f sck = 1 mhz ? ? 0.3 ma f sck = 4 mhz ? ? 1.2 ma f sck = 16 mhz ? ? 3.2 ma i sb v dd standby current cs = v dd . all other inputs v ss or v dd . t a = 85 c ? ? 10 ? a t a = 125 c ? ? 30 ? a i li input leakage current v ss < v in < v dd ??1 ? a i lo output leakage current v ss < v out < v dd ??1 ? a v ih input high voltage 0.75 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.25 v dd v v oh output high voltage i oh = ?2 ma v dd ? 0.8 ? ? v v ol output low voltage i ol = 2 ma ? ? 0.4 v v hys [5] input hysteresis (cs and sck pin) 0.05 v dd ??v notes 3. electrostatic discharge voltages specified in the datasheet are the aec-q100 standard limits used for qualifying the device. to know the maximum value device passes for, please refer to the device qualification report available on the website. 4. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 5. this parameter is characterized but not 100% tested.
cy15e064q document number: 002-10028 rev. *b page 12 of 20 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times ...................................................5 ns input and output timing reference levels ................0.5 v dd output load capacitance .............................................. 30 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 125 ? c 11000 ? hours t a = 105 ? c11?years t a = 85 ? c 121 ? nv c endurance over operating temperature 10 13 ? cycles example of an f-ra m life time in an aec-q100 automotive application an application does not operate under a steady temperature for t he entire usage life time of the application. instead, it is of ten expected to operate in multiple temperature environments throughout the application?s usage life time. accordingly, the retention specif ication for f-ram in applications often needs to be calculated cumulative ly. an example calculation for a multi-temperature thermal pro files is given below. tempeature t time factor t acceleration factor with respect to tmax a [6] profile factor p profile life time l (p) t1 = 125 ? c t1 = 0.1 a1 = 1 8.33 > 10.46 years t2 = 105 ? c t2 = 0.15 a2 = 8.67 t3 = 85 ? c t3 = 0.25 a3 = 95.68 t4 = 55 ? c t4 = 0.50 a4 = 6074.80 a lt ?? ltmax ?? ------------------------ e ea k ------- 1 t --- 1 tmax --------------- - ? ?? ?? == p 1 t1 a1 ------- t2 a2 ------- t3 a3 ------- t4 a4 ------- +++ ?? ?? ------------------------------------------------------- - = lp ?? pltmax ?? ? = capacitance parameter [7] description test conditions max unit c o output pin capacitance (so) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter description test conditions 8-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 147 ? c/w ? jc thermal resistance (junction to case) 47 ? c/w notes 6. where k is the boltzmann constant 8.617 10 -5 ev/k, tmax is the highest temperature specified for the product, and t is any temperature within the f-ram product specification. all temperatures are in kelvin in the equation. 7. this parameter is characterized but not 100% tested.
cy15e064q document number: 002-10028 rev. *b page 13 of 20 ac switching characteristics over the operating range parameters [8] description min max min max unit cypress parameter alt. parameter f sck ? sck clock frequency 0 4 0 16 mhz t ch ? clock high time 100 ? 25 ? ns t cl ? clock low time 100 ? 25 ? ns t csu t css chip select setup 100 ? 10 ? ns t csh t csh chip select hold 100 ? 10 ? ns t od [9, 10] t hzcs output disable time ? 100 ? 20 ns t odv t co output data valid time ? 75 ? 25 ns t oh ? output hold time 0 ? 0 ? ns t d ? deselect time 100 ? 60 ? ns t r [11, 12] ? data in rise time ? 50 ? 50 ns t f [11, 12] ? data in fall time ? 50 ? 50 ns t su t sd data setup time 30 ? 5 ? ns t h t hd data hold time 20 ? 5 ? ns t hs t sh hold setup time 70 ? 10 ? ns t hh t hh hold hold time 40 ? 10 ? ns t hz [9, 10] t hhz hold low to hi-z ? 100 ? 20 ns t lz [10] t hlz hold high to data active ? 50 ? 20 ns notes 8. test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 30 pf load capacitance shown in ac test conditions on page 12 . 9. t od and t hz are specified with a load capacitance of 5 pf. transiti on is measured when the outputs enter a high impedance state. 10. this parameter is characterized but not 100% tested. 11. rise and fall times measured between 10% and 90% of waveform. 12. these parameters are guaranteed by design and are not tested.
cy15e064q document number: 002-10028 rev. *b page 14 of 20 figure 13. synchronous data timing (mode 0) figure 14. hold timing hi-z valid in hi-z cs sck si so t cl t ch t csu t su t h t odv t oh t d t csh t od valid in valid in cs sck hold so t hs t hz t lz t hh t hs t hh ~ ~ ~ ~ si t su valid in valid in
cy15e064q document number: 002-10028 rev. *b page 15 of 20 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (cs low) 1 ? ms t pd last access (cs high) to power-down (v dd (min)) 0 ? s t vr [13] v dd power-up ramp rate 30 ? s/v t vf [13] v dd power-down ramp rate 20 ? s/v figure 15. power cycle timing cs ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) note 13. slope measured at any point on v dd waveform.
cy15e064q document number: 002-10028 rev. *b page 16 of 20 ordering code definitions ordering information ordering code package diagram package type operating range cy15e064q-sxe 51-85066 8-pin soic automotive-e CY15E064Q-SXET 51-85066 8-pin soic all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. option: x = blank or t blank = standard; t = tape and reel temperature range: e = automotive-e (?40 ? c to +125 ? c) x = pb-free package type: s = 8-pin soic q = spi f-ram density: 064 = 64-kbit voltage: e = 4.5 v to 5.5 v f-ram company id: cy = cypress 15 cy e 064 q s x e x -
cy15e064q document number: 002-10028 rev. *b page 17 of 20 package diagram figure 16. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *h
cy15e064q document number: 002-10028 rev. *b page 18 of 20 acronyms document conventions units of measure acronym description aec automotive electronics council cpha clock phase cpol clock polarity eeprom electrically erasable programmable read-only memory eia electronic industries alliance i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit f-ram ferroelectric random access memory rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm kbit kilobit kv kilovolt mhz megahertz ? a microampere ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy15e064q document number: 002-10028 rev. *b page 19 of 20 document history page document title: cy15e064q, 64-kbit (8 k 8) serial (spi) automotive f-ram document number: 002-10028 rev. ecn no. orig. of change submission date description of change ** 5023918 gvch 12/02/2015 new data sheet. *a 5568261 gvch 01/27/2017 changed stat us from preliminary to final. updated maximum ratings : updated electrostatic discharge voltage (in compliance with aec-q100 standard): changed value of ?human body model? from 4 kv to 2 kv. changed value of ?charged device model? from 1.25 kv to 500 v. removed machine model related information. updated ordering information : updated part numbers. updated to new template. *b 5693278 gvch 04/12/2017 updated maximum ratings : added note 3 and referred the same note in ?electrostatic discharge voltage?. updated to new template.
document number: 002-10028 rev. *b revised april 12, 2017 page 20 of 20 cy15e064q ? cypress semiconductor corporation, 2015?2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support

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